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Senior Signal Integrity (SI) Engineer High-Speed PCIe / SSD | Contract | Santa Clara, CA

Anagha Techno SoftSanta Clara, CA🇺🇸United StatesPosted Oct 7, 2026

Quick Overview

Seniority
Mid Senior
Work mode
On Site
Location
Santa Clara, CA, United States
Posted
Yesterday
ANSYSPCB Design

Job Description

Senior Signal Integrity (SI) Engineer High-Speed PCIe / SSD | Contract | Santa Clara, CA
Senior Signal Integrity (SI) Engineer High-Speed PCIe / SSD
Job Type: Contract-to-Hire
Location: Santa Clara, CA Onsite, 5 Days/Week
Experience: 5+ Years
Job Summary
We are seeking a highly skilled Senior Signal Integrity (SI) Engineer to support high-speed hardware platforms and enterprise storage/SSD products.
The ideal candidate will have strong hands-on experience in high-speed signal integrity analysis, PCIe channel simulation, TDR/S-parameter measurements, 3D electromagnetic simulation, PCB stackup and via optimization, and IBIS/IBIS-AMI modeling.
Key Responsibilities
  • Own high-speed signal integrity analysis from hardware architecture through production.
  • Drive board-level SI decisions involving PCB materials, stackups, via structures, channel loss, and optimization.
  • Perform SI simulations including insertion loss, return loss, crosstalk, TDR, impedance, and channel analysis.
  • Lead hands-on TDR and S-parameter measurements, including calibration and de-embedding.
  • Perform 3D electromagnetic extraction and simulation for vias, connectors, and complex channel structures.
  • Correlate simulation results with laboratory measurements and refine models.
  • Develop and customize IBIS and IBIS-AMI models for PCIe and other high-speed interfaces.
  • Perform high-speed eye diagram, jitter, and margin analysis.
  • Support hardware debug activities involving signal integrity issues.
  • Perform Power Integrity (PI) simulations and analysis.
  • Collaborate with PCB, hardware, firmware, mechanical, thermal, and test engineering teams.
  • Develop SI design guidelines, methodologies, and best practices.
  • Provide technical guidance and mentorship to junior engineers.
Required Qualifications
  • 5+ years of experience in high-speed Signal Integrity engineering.
  • Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
  • Strong hands-on PCIe signal integrity simulation and channel analysis experience.
  • Hands-on experience with TDR and S-parameter measurements.
  • Experience with measurement calibration and de-embedding.
  • Strong understanding of high-speed PCB design, including materials, stackups, vias, impedance, and channel loss.
  • Strong hands-on experience with Simbeor for 3D-EM extraction and simulation.
  • Experience with IBIS / IBIS-AMI models.
  • Experience with eye diagrams, jitter, margin, and high-speed channel analysis.
  • Strong understanding of SI/PI design tradeoffs.
  • Excellent analytical, troubleshooting, communication, and cross-functional collaboration skills.
  • Ability to work independently in a fast-paced hardware development environment.
Preferred Skills
  • Enterprise SSD / storage hardware
  • NAND
  • NVMe
  • PCIe Gen4 / Gen5 / Gen6
  • DDR
  • Ansys HFSS / SIwave
  • Cadence Sigrity
  • HyperLynx
  • Keysight ADS
  • Power Integrity / PDN analysis
  • MATLAB or Python

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