Principal Digital Engineer - FPGA / ASIC / High-Speed Design with Security Clearance

Principal Digital Engineer - FPGA / ASIC / High-Speed Digital Design Location: Woodland Hills, CA
Work Arrangement: On-site
Schedule: 9/80
Clearance: Active DoD Secret clearance required
Citizenship: U.S. citizenship required Position Overview We are seeking a Principal Digital Engineer to support the design and verification of digital systems for a safety-critical defense program. This role focuses on high-speed digital design, FPGA, SoC, and ASIC implementation, and hardware verification.

You will work across the engineering lifecycle, from requirements definition and conceptual design through detailed design, verification, and production transition. The engineer will collaborate with program leadership, scientists, hardware engineers, and manufacturing teams to develop next-generation navigation, video, and cockpit systems. Responsibilities Design and verify high-speed digital systems for safety-critical applications. Support FPGA, SoC, and ASIC development, including RTL design, synthesis, and timing closure.

Develop and review digital hardware designs using VHDL and/or Verilog. Define and manage hardware requirements throughout the development lifecycle. Contribute to conceptual design, detailed design, verification, and production transition. Apply digital design and verification methods to ensure systems meet performance and reliability requirements. Collaborate with engineering teams, program leadership, and manufacturing organizations. Support the integration of appropriate engineering processes, tools, and verification methods.

Contribute to the development of advanced navigation, video, and cockpit products.

Basic Qualifications Bachelor's degree in a STEM field with 5 years of relevant experience, a master's degree with 3 years of relevant experience, or a Ph. D. in a STEM field with 1 year of relevant experience. Experience with high-speed digital design and verification. Experience with FPGA, SoC, or ASIC implementation. Experience with VHDL or Verilog, synthesis, and timing closure. Experience with hardware requirements definition, conceptual design, detailed design, verification, and production transition. Active U.S. Government Secret clearance. U.S. citizenship. Ability to work on-site full-time in Woodland Hills, CA.

Preferred Qualifications Experience with SystemVerilog, Universal Verification Methodology (UVM), or hardware-in-the-loop testing. Knowledge of computer architecture, including bus standards, interrupts, and memory. Experience with model-based engineering using MATLAB or Simulink. Knowledge of fixed-point and floating-point implementations. Experience with sensors and digital signal processing. Experience with safety-critical hardware design and DO-254. Cost Account Management (CAM) certification or experience. Strong communication, collaboration, team-building, and facilitation skills. This opportunity is suited for a digital hardware engineer with strong FPGA, ASIC, or SoC design experience and a background in high-speed digital design, verification, and safety-critical systems.