Physical Design Engineer

WE'RE HIRING | PHYSICAL DESIGN ENGINEERS
Locations: San Jose, CA / San Diego, CA / Irvine, CA
Experience: 12+ Years
Employment Type: Full-Time
We are looking for experienced Physical Design Engineers with strong expertise in ASIC/SoC Physical Design and end-to-end RTL-to-Tape-out implementation.
Key Responsibilities:
Execute end-to-end Physical Design, Synthesis, Physical Verification, and Timing Closure.
Perform RTL synthesis and Static Timing Analysis (STA).
Execute Place & Route (P&R) and Clock Tree Synthesis (CTS).
Handle timing closure, skew balancing, and insertion delay optimization.
Perform floorplanning, layout, and top-level STA.
Conduct EM/IR analysis and physical verification.
Contribute to physical design flow and methodology development.
Collaborate with IC Design and RTL Engineering teams.
Required Skills:
Strong hands-on experience with Cadence Innovus.
Complete Physical Design experience from RTL to Tape-out.
Expertise in Synthesis, STA, Timing Closure, P&R, CTS, and Floorplanning.
Experience with Physical Verification and EM/IR Analysis.
Strong TCL and/or PERL scripting skills.
Proficiency in industry-standard EDA tools.
Excellent communication and collaboration skills.

Education: Bachelor's degree in Electrical Engineering, Electronics Engineering, or a related field.
Preferred Qualifications:
Deep expertise in top-level floorplanning and STA.
Proven experience delivering complex ASIC/SoC designs through successful tape-out.