CPU Physical Design Hardware Engineer

Qualcomm seeks a CPU Physical Design Engineer to develop high performance, low power CPU cores for advanced wireless and 5G SoCs. You will own RTL to GDSII implementation, including floorplanning, place and route, clock tree synthesis, static timing analysis, power optimization, and physical verification. Collaborate with architecture, RTL, and verification teams to close timing, area, and power on aggressive schedules. Use industry standard EDA tools and cutting edge process technologies to deliver silicon that powers smartphones, IoT, automotive, and AI platforms in a fast paced, innovative environment.

Responsibilities

• Drive RTL-to-GDSII CPU physical implementation from floorplanning through signoff
• Perform place and route, clock tree synthesis, and congestion optimization
• Run static timing analysis to close timing across multiple corners and modes
• Optimize power, performance, and area for advanced process nodes
• Execute physical verification (DRC, LVS) and coordinate fixes with layout teams
• Collaborate with architecture, RTL, and verification teams on design tradeoffs
• Develop and maintain physical design flows, scripts, and methodologies
• Debug implementation issues and support silicon bring-up as needed

Required Skills

• CPU physical design
• ASIC implementation
• RTL-to-GDSII flow
• Floorplanning
• Place and route
• Clock tree synthesis (CTS)
• Static timing analysis (STA)
• Power, performance, area optimization (PPA)
• Physical verification (DRC/LVS)
• EDA tools (Cadence/Synopsys/Mentor)