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DFT (Design for Test) Engineer.

INFT Solutions incSanta Clara, CA🇺🇸United StatesPosted 21 Jul 2026

Why This Role Stands Out

This hybrid role at INFT Solutions offers a fantastic opportunity to deepen your expertise in Design for Test, working with leading industry tools and contributing to innovative semiconductor solutions. You'll thrive here if you have a strong foundation in DFT fundamentals and hands-on experience with tools like Siemens Tessent, as you'll be instrumental in driving testability and quality in cutting-edge designs. Seize this chance to advance your career in a dynamic environment.

Quick Overview

Work Type
Hybrid
Level
Mid Senior

Job Description

DFT (Design for Test) Engineer.

Location: Santa Clara, CA

Key Skills & Experience

  • Hands-on experience with the Siemens Tessent (Mentor Graphics) DFT tool suite.
  • Strong understanding of DFT fundamentals, including controllability, observability, scan insertion, and scan-based testing.
  • Expertise in ATPG (Automatic Test Pattern Generation), including pattern generation, analysis, debugging, and fault coverage improvement.
  • Experience with MBIST (Memory Built-In Self-Test), including memory test architecture, implementation, and diagnostics.
  • Good knowledge of IO Test methodologies for interface and pin-level validation.
  • Strong understanding of Clock DFT and clock verification concepts.
  • Solid foundation in Digital Design and RTL (Verilog/SystemVerilog).
  • Experience with industry-standard DFT/ATPG EDA tools.
  • Experience in verification of DFT features, including Boundary Scan (JTAG), IJTAG, MBIST, High-Speed Scan Testing, and other DFT methodologies.
  • Excellent analytical, debugging, and problem-solving skills.

Skills

Verilog

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