Physical Design Engineer (Top-Level / Full-Chip) - AS

Title: Physical Design Engineer/ ASIC Implementation Engineer (Strong Top-Level / Full-Chip Physical Design and Implementation experience)
Location: San Jose, CA (Onsite role)
Type: FTE Permanent role

Note from Hiring manager: 
Candidate either should have good experience on Chip level/Top level design Or if they are extremely strong in one of the other aspects of design e.g. STA (Static Timing Analysis) or Floor Planning in chip design, they can still be considered.

Only in those cases where you are absolutely certain about candidate's relocation commitment, initial round can be held over zoom but the final round would be in-person only.

Job Description:
Client is searching for a Physical Design Engineer to join the ASIC Products Division. 
This position involves working with the latest technology to continue driving next generation AI designs. 
This position will require in-depth knowledge and expertise in Physical Design aspects of taking Netlist to silicon tape-out.

Responsibilities include, but are not limited to the following:
Execution of Physical Design, Physical Verification, and Timing Closure
Timing closure through various methods and strategies; preferable in-depth experience in top-level STA
EM/IR Analysis, Place and Route
Clock Tree Synthesis; experience with custom clock trees, insertion reduction and skew balancing techniques
Floor-planning and Layout; preferable in-depth experience in top-level floorplanning
Flow and Methodology Development
Collaborating with IC Design RTL Engineers

Required attributes:
TCL/PERL Scripting
Proficiency in related EDA Tools
Full physical design cycle experience: RTL to Tape-out
Excellent verbal and written communication skills

Education and Experience Requirements:
Minimum: Bachelor’s degree required in Electrical Engineering or Electronics Engineering
8+ Years of relevant experience