Why This Role Stands Out
This hybrid DFX Engineer role at Momento USA offers a fantastic opportunity to hone your skills on cutting-edge SoCs and ASICs within a collaborative environment. You'll thrive here if you're a motivated mid-senior engineer eager to contribute to robust manufacturability and silicon quality, so be sure to apply!
Quick Overview
Job Description
Momento USA is a global technology consulting, talent acquisition, and creative development firm that addresses clients' most pressing needs and challenges. We are currently looking for a DFT/DFX Engineer
Position: DFT/DFX Engineer
Location: Bay Area, CA
Long Term
JD: We are looking for a highly motivated DFX Engineer to develop, implement, verify, and validate advanced Design-for-Test (DFT/DFX) solutions for complex SoCs and ASICs. The candidate will work closely with Architecture, Design, Verification, Physical Design, and Post-Silicon teams to ensure robust manufacturability, testability, and silicon quality.
Key Responsibilities
- Create and execute test plans for DFX features including Scan, MBIST, SSN, EDT, IJTAG, and JTAG.
- Verify DFX implementations at IP, subsystem, and SoC levels.
- Develop SystemVerilog/UVM based verification environments and test benches.
- Debug regression failures and identify root causes related to design or verification.
- Generate and validate Scan/ATPG patterns for production testing.
- Collaborate with cross-functional teams including Design, Architecture, Physical Design, Validation, and ATE teams.
- Automate DFX flows using scripting languages and improve overall test methodologies.
- Contribute to DFX architecture planning and implementation for next-generation SoCs.
Required Technical Skills
- DFX / DFT
- Scan Insertion & Compression
- ATPG Pattern Generation & Debug
- MBIST / LBIST
- JTAG, IEEE 1500, IEEE 1687 (IJTAG)
- SSN (Streaming Scan Network)
EDA Tools
- Siemens Tessent Suite (TestKompress, MBIST, SSN, IJTAG, EDT)
- Synopsys Fusion Compiler
- Synopsys Design Compiler
- SpyGlass
- RTL and Gate-Level Simulation Tools
Verification
- SystemVerilog
- UVM
- Assertions (SVA)
- Functional and Code Coverage
- SoC/IP Verification
- Python/Perl, TCL/Shell Scripting
Preferred Qualifications
- Experience in end-to-end DFX flow development.
- Strong understanding of ASIC/SoC design flow from RTL to silicon.
- Exposure to high-speed interfaces such as PCIe, DDR, Ethernet, USB, CXL, UCIe, or SerDes is a plus.
Educational Qualification: B.E./B.Tech/M.E./M. Tech in Electronics, Electrical Engineering, VLSI, Computer Engineering, or related fields.
Thanks,
Adam Walker (Aquib)
Technical Recruiter
Momento USA | Exceeding Customer Expectations…
440 Benigno Blvd, Unit#A 2nd Floor. Bellmawr, NJ 08031
Interstate Business Park
Direct: || Tel : Ext 1021; Fax:
Email: ; Web: .
Note: Momento USA is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.
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