FPGA Design / Verification Engineer
Why This Role Stands Out
As an FPGA Design/Verification Engineer at Sun Technologies, Inc., you'll contribute to cutting-edge R&D programs, developing innovative solutions for space missions and enjoying a competitive hourly rate of $100. This role is ideal for mid-senior engineers skilled in high-speed digital design and verification, eager to enhance FPGA development efforts and collaborate across disciplines. Apply today to join a team building leading-edge products for future growth.
Quick Overview
Job Description
Job Title: FPGA Design/Verification Engineer
Duration: up to 6 months contract with possible extension
Location: Littleton, CO
Work Schedule: 5/10 – 1st Shift, Monday to Friday; 8 hours per day.
Pay Rate: $100/hr on W2 [the pay rate may differ depending on your skills, education, experience, and other qualifications]
Featured Benefits:
· Medical Insurance in compliance with the ACA
· 401(k)
· Sick leave in compliance with applicable state, federal, and local laws
Job Description:
· The selected candidate will be responsible for FPGA development on R&D program.
· This engineer with have experience in developing, testing, and integrating high speed digital design, high speed communication and system-on-chip (SOC) implemented on FPGA platforms.
· This person will help develop more affordable ways to automate and develop scripts to improve FPGA development efforts on ground test equipment for space missions.
· Cross discipline collaboration with Test, Integration, Software, Systems Architects and Digital Circuit designers to create leading edge products for future business growth, contributing to complex systems employing high speed networking concepts.
· Overall contribution to design, simulation, verification, integration & test of complex, high speed products. Onsite, Denver CO.
Skills Required:
· Candidate with Spacewire experience is required.
· Experience with Python also is required.
· Experience with Xilinx Ultrascale FPGA platforms, Xilinx Vivado tool suite required.
· Must be fluent in VHDL language (additional knowledge of Verilog/SystemVerilog a plus).
Skills
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