ASIC Verification Engineer

RESPONSIBILITIES

Kforce is immediately seeking an experienced ASIC Verification Engineer to support our enterprise networking and cloud solutions customer based in Carlsbad, CA.

Summary

We are seeking a collaborative Design Verification Engineer with 5-12 years of industry experience to help create cutting edge System-on-Chip (SoC) designs delivered first time right. The ASIC Verification Engineer will work in a collaborative environment, participating in architectural decisions and verification strategies that directly impact product success. Our team values diverse perspectives and creative problem-solving approaches to deliver exceptional customer experiences.

Responsibilities

• Develop and implement Universal Verification Methodology (UVM) based verification environments
• Create comprehensive verification plans at both block and system levels
• Design and implement verification components including assertions, traffic generators, agents, and scoreboards
• Collaborate with cross-functional teams to evaluate design testability and verification requirements
• Lead debug efforts and provide solutions for complex technical challenges

REQUIREMENTS

• Bachelor's degree in Electrical Engineering or a related field
• UVM Based testbench development experience
• Experience in ASIC or SOC verification
• Demonstrated experience in developing test plans and verification infrastructure
• Practical knowledge of verification methodologies from block level to system level
• Proficiency in System Verilog
• Experience in identifying and resolving complex design and verification issues
• Timing and gate level simulation experience
• C coding for firmware delivery for post silicon bringup experience

Preferred Qualifications

• Bachelor's/Master's degree in Electrical or Communications Engineering or a related field
• Experience with formal verification techniques including abstraction and end-to-end checking
• Experience with industry-standard tools and scripting languages (Python or Perl) for automation
• System Verilog coding and debug experience
• AI based CAD efficiency improvisation initiatives High speed serial protocols preferred UCIe, PCIE, etc.
• Analog debug experience including DAC/ADC & calibrations white-box verification

The pay range is the lowest to highest compensation we reasonably in good faith believe we would pay at posting for this role. We may ultimately pay more or less than this range. Employee pay is based on factors like relevant education, qualifications, certifications, experience, skills, seniority, location, performance, union contract and business needs. This range may be modified in the future.

We offer comprehensive benefits including medical/dental/vision insurance, HSA, FSA, 401(k), and life, disability & ADD insurance to eligible employees. Salaried personnel receive paid time off. Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a Service Contract Act project are eligible for paid sick leave.

Note: Pay is not considered compensation until it is earned, vested and determinable. The amount and availability of any compensation remains in Kforce's sole discretion unless and until paid and may be modified in its discretion consistent with the law.

This job is not eligible for bonuses, incentives or commissions.

Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.

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