ASIC Physical Design Engineer / RTL Synthesis Engineer

This is Ganesh from DELLA INFOTECH INC. We have an outstanding opening for you for the opportunity below. Please check the job description and share your updated resume, if you are interested.

Hiring: Senior ASIC RTL-to-Physical Design (RTL2PD) / RTL Synthesis Engineer

Location: San Jose, CA(onsite)

Experience: 8 to 12 years

What will Be Doing:

• RTL Synthesis, Constraint writing, validation, Static timing Analysis
• Writing Scripts/Modiying scripts for RTL synthesis, SDC creation, STA
• Debug synthesis issues and STA
• Generate clean netlist.

What we are looking for:

• Experience: 8 12 years of hands-on RTL Synthesis
• EDA exposure: Design compiler, PrimeTime, Tempus, Genus,
• Multi-Node Design: Experience working with 16nm, 7nm etc nodes.

MUST HAVE : RTL Synthesis, Constraint writing, validation, Static timing Analysis

• Need Design Engineer with very strong experience Timing Constraints Writing.
• RTL to Physical Design (RTL2PD) stage experience
• RTL2PD Design Engineer(ASIC)