FPGA Firmware Engineer

Location: Westminster, CO Salary: $140,000.00 USD Annually - $155,000.00 USD Annually Description: Our client is currently seeking an FPGA Firmware Engineer

FPGA Firmware Engineer

Location: Westminster, CO

Full Time

Role Overview

• We are a leading Space Surveillance and Intelligence company focused on ensuring orbital safety and sustainability. With expertise in space-based detection, tracking, identification, and monitoring, we provide comprehensive domain awareness across regimes, allowing end users to have actionable intelligence on a single platform. At the core of our infrastructure lies a sophisticated integration of hardware and software capabilities aligned with the key principles of situational awareness: perception (data collection), comprehension (data processing), and prediction (analytics). This holistic approach empowers us to monitor all Resident Space Objects (RSOs) in orbit, fostering comprehensive domain awareness.
• We are seeking an experienced and driven FPGA Firmware Engineer to own digital design and embedded firmware for our electro-optical/infrared (EOIR) and related payloads. This is a build role that encompasses FPGA logic design and verification, firmware development on AMD Versal SoC and comparable architectures, microcontroller firmware, and the detector, sensor, and high-speed data interfaces these payloads depend on. You will work closely with electrical, optical, and mechanical engineers through board bring-up and integration, taking responsibility for the correctness, timing, and reliability of the payload's digital and firmware elements from architecture through hardware validation.
• By joining us, you will be part of a collaborative, innovative, and mission-focused environment where your ideas and skills have a significant, real-world impact. You will have the opportunity to shape company culture, set the foundation for future success, and build world-class teams, all while receiving a competitive salary, benefits, and equity package.

Key Responsibilities

• Design, implement, and verify FPGA logic (RTL) for EOIR and other payloads on AMD Versal adaptive SoC and comparable architectures.
• Develop embedded firmware across the payload stack, including the Versal processing system, supporting microcontrollers, boot and configuration, and device drivers.
• Design and bring up detector-readout and sensor interfaces (focal-plane arrays / ROICs), including timing, control, and calibration paths.
• Implement high-speed data interfaces and onboard signal and image-processing chains (SerDes, CameraLink/CoaXPress/MIPI, SpaceWire/SpaceFibre; framing, corrections, compression).
• Lead board bring-up and hardware/firmware integration, debugging at the boundary between hardware and firmware.
• Integrate third-party and vendor IP cores, and coordinate with external developers and vendors to keep payload deliveries on schedule.
• Maintain traceability from FPGA and firmware designs to top-level system requirements, and ensure designs meet applicable safety and performance standards.
• Own verification processes, including testbenches, simulation, timing closure, and hardware-in-the-loop validation.
• Contribute to payload architecture, interface definition, and processor/component selection trades.

Minimum qualifications:

• Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• 5+ years of experience developing FPGA logic and firmware for payloads, instruments, or other high-reliability embedded systems.
• Strong RTL design experience in VHDL or Verilog, including real verification experience and timing closure on AMD/Xilinx toolchains (Vivado/Vitis) and simulation tools (e.g., ModelSim/QuestaSim).
• Experience developing embedded firmware in C/C++ on SoC and microcontroller targets (bare-metal and/or RTOS).
• Direct experience with AMD Versal, Zynq, or Zynq UltraScale+-class adaptive SoCs (or comparable architectures).
• Experience with sensor/detector interfacing, high-speed data interfaces, and on-FPGA DSP or image-processing chains.
• Experience with hardware and ARM-based SoC bring-up and lab debugging, including the use of oscilloscopes, logic analyzers, protocol analyzers, and schematic reading.
• Must be able to obtain and maintain a U.S. security clearance.

Preferred qualifications:

• Experience with EOIR or imaging payloads, specifically focal-plane arrays, ROICs, IR detectors, and radiometric calibration.
• Experience in space or high-reliability environments, including rad-tolerant/rad-hard components and FPGA SEU mitigation (TMR, configuration scrubbing).
• Familiarity with SpaceWire/SpaceFibre, CCSDS, or comparable spacecraft data-handling standards.
• Experience implementing image/video compression or ML inference on FPGA.
• Familiarity with hardware/firmware assurance standards (e.g., DO-254, NASA NPR 7150.2).
• Prior experience working on government R&D programs.

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