DFT Engineer

Hi,

Job Title : Senior DFT Engineer [ATPG , MBIST, IO Test, Clock Verification]

Location : Santa Clara, CA

Experience : 4+ Years in DFT

Required Skills & Qualifications

• 4+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs
• Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing
• Proven expertise in ATPG pattern generation, analysis, and debug
• Experience with MBIST, including memory test architectures and diagnostics
• Knowledge of IO Test methodologies for interface and pinlevel validation
• Solid understanding of clock DFT and clock verification concepts
• Strong grasp of digital design and RTL fundamentals
• Experience with industrystandard DFT/ATPG EDA tools
• Ability to work effectively in fastpaced, highperformance semiconductor programs
• Strong analytical, problemsolving, and communication skills

Preferred Qualifications

• B-Tech , BE or equivalent degree in Electronics domain.
• Experience with silicon bring-up and production test support
• Exposure to advanced nodes and complex SoC & GPU architectures
• Exposure to lowpower and performanceaware DFT techniques
• Experience supporting highvolume production and yield optimization
• Knowledge of low-power and performance-aware DFT techniques
• Experience working in high-volume manufacturing environments

If you are interested in this opportunity, please submit your updated resume in MS Word format along with your expected hourly rate to [Insert contact email or Phone #].

Rick P

Tel: Fax:  
300 N Coit Rd., # 340
Richardson, TX 75080
Web: CompNova.com