Why This Role Stands Out
This hybrid role offers a fantastic opportunity to contribute to cutting-edge enterprise networking and cloud solutions, developing innovative DFT IP and driving testability strategies for new silicon devices. You'll thrive here if you're a mid-senior engineer with extensive experience in DFT implementation, simulation, and post-silicon debug, eager to leverage your expertise in a collaborative environment. Apply now to join a leading customer and make a significant impact on their next generation of products.
Quick Overview
Job Description
RESPONSIBILITIES
Kforce is immediately seeking an experienced ASIC Design for Test Consulting Engineer to remotely support our enterprise networking and cloud solutions customer based in Carlsbad, CA.
Responsibilities
- Responsible for implementing the Hardware Design-for-Test (DFT) features - scan, mbist, BISR, boundary scan, setting up/debugging DFT simulations and supporting post-silicon testing/debug
- Responsible for development of innovative DFT IP in collaboration with the multi-functional teams, and play a key role in full chip design integration with the testability features coordinated in the RTL
- Along with the DFT team, you will participate in the creation of Innovative Hardware DFT & physical design aspects for new silicon device models, bare die & stacked die, driving re-usable test and debug strategies
REQUIREMENTS
- Bachelor's or a Master's degree in Electrical or Computer Engineering required, with at least 8-10 years of experience
- Experience with Jtag protocols, Scan and BIST architectures, including memory BIST, boundary scan and integrating 3rd party IP's and high-speed digital/analog macros
- Experience with ATPG and EDA tools like Tessent tool sets, Xcelium, Genus, TempPrimetime
- At least one project with hands-on post-silicon debug of DFT patterns - scan, mbist, boundary scan and release to production
- The ability to craft solutions and debug with minimal mentorship
Nice to Have
- Excellent communication and presentation skills
- Strong attention to detail and system level understanding of networking and photonic solutions
- Strong ability to establish/refine, train teams on DFT methodologies - from design phase to high volume production
- Ability to quickly learn new concepts and adapt to evolving technologies
The pay range is the lowest to highest compensation we reasonably in good faith believe we would pay at posting for this role. We may ultimately pay more or less than this range. Employee pay is based on factors like relevant education, qualifications, certifications, experience, skills, seniority, location, performance, union contract and business needs. This range may be modified in the future.
We offer comprehensive benefits including medical/dental/vision insurance, HSA, FSA, 401(k), and life, disability & ADD insurance to eligible employees. Salaried personnel receive paid time off. Hourly employees are not eligible for paid time off unless required by law. Hourly employees on a Service Contract Act project are eligible for paid sick leave.
Note: Pay is not considered compensation until it is earned, vested and determinable. The amount and availability of any compensation remains in Kforce's sole discretion unless and until paid and may be modified in its discretion consistent with the law.
This job is not eligible for bonuses, incentives or commissions.
Kforce is an Equal Opportunity/Affirmative Action Employer. All qualified applicants will receive consideration for employment without regard to race, color, religion, sex, pregnancy, sexual orientation, gender identity, national origin, age, protected veteran status, or disability status.
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