Quick overview
Job description
Qualifications
- 4+ years experience in high performance analog layout in advance CMOS process nodes
- Experience with layouts of high performance analog blocks (such as ADC, DAC, PLL, and SERDES, for example)
- Experience with analog layout techniques such as common centroid, interdigitation, shielding, dummy devices, EM aware routing on critical block, and must be versed with with VXL compliant methodology
- Familiarity in various physical verification checks DRC, LVS, DFM, ERC, EM, IR etc.
- Layout Automation using SKILL/PERL/Python is a plus
- Self starter with the ability to define and adhere to schedule and methodology
- Must possess strong social skill and be an excellent team mate
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