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Full time
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CI

Design Verification Engineer

CirrusAustin🇺🇸United StatesPosted Apr 15, 2026

Why This Role Stands Out

This hybrid role at Cirrus Logic offers significant opportunities to develop advanced verification methodologies while collaborating with top engineering teams on cutting-edge mixed-signal IC solutions. You'll thrive here if you're a mid-senior engineer eager to contribute to end-to-end functional verification across diverse domains in a supportive and inclusive environment. Apply now to grow your career with a company renowned for its award-winning culture and impactful work.

Quick Overview

Seniority
Mid Senior
Employment type
Full Time
Work mode
Hybrid
Location
Austin, United States
Posted
5 months ago

Job Description

For over four decades, Cirrus Logic has been propelled by the top engineers in mixed-signal processing. Our rockstar team thrives on solving complex challenges with innovative end-user solutions for the world's top consumer brands. Cirrus Logic is also known for its award-winning culture, which was built on a foundation of inclusion and fairness, meaningful community engagement, and delivering enjoyable employee experiences at every turn. But we couldn’t do it without our extraordinary workforce – and that’s where you come in. Join our team and help us continue to make Cirrus Logic an exceptional place to grow your career! 

We are seeking an experienced and innovative Design Verification Engineer to join a world-class silicon design verification team. This role partners closely with digital and analog designers, systems and applications engineers, firmware/software teams, and manufacturing test to deliver high-quality mixed-signal IC solutions. You will be responsible for end-to-end functional verification across block-level and chip-level designs, contributing to advanced verification methodologies and infrastructure.

This position offers exposure to multiple verification domains including UVM-based testbench development, formal verification, hardware emulation/acceleration, gate-level simulations, and software-driven verification in a highly collaborative and technically rigorous environment. 

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