Post Silicon Validation Engineer

Post Silicon Validation Engineer

• Location: Sunnyvale, CA
• Hybrid

We need senior profiles who have RTL experience, Embedded FW Development and debug, ARM SoC, Display/Graphics related experience. Engineer does not need to have ML-coprocessor background. Display domain is more important. 

Job Description:

• Validate display SOC, Mixed Signal SOC, and IP. (good)
• Define validation strategy and test plans for new IP blocks, aligning with RTL, architecture, FW. (good)
• Develop silicon validation infrastructure and coding C/C++ and Python for emulation (Zebu), FPGA (HAPS), and first silicon platforms.  Identify risks and develop mitigation strategies. (Good)
• Execute bring-up/debug, workload enablement, and SW stack validation. (Must)
• Perform performance and power characterization. (Must)
• Create automated data collection flows and convert large datasets into executive summaries. (Must)
• Track test coverage, document bugs, drive cross-functional debug, and verify silicon fixes. (Must)
• Participate in design reviews and provide recommendations to strengthen validation coverage. (Good)
• Collaborate with factory test teams to align validation and production characterization strategies. (Must)