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Senior ASIC/SoC RTL Design Engineer RTL Design Analysis

AIT Global, Inc.San Diego, CA🇺🇸United States

Quick overview

SeniorityMid Senior
Work modeOn Site
LocationSan Diego, CA, United States
Verilog

Job description

Job Title: Senior ASIC/SoC RTL Design Engineer RTL Design Analysis
Location: San Diego, CA
Role Overview:
We are seeking an experienced Senior RTL Design Engineer to support an ASIC/SoC RTL reverse engineering project in San Diego, California. The ideal candidate will have strong expertise in RTL design, digital logic, and SoC architecture, with the ability to analyze existing hardware designs and understand their functionality and implementation.
The selected candidate must be willing to relocate temporarily to San Diego for approximately 2 3 months to support on-site project activities and collaborate closely with the engineering team.
Key Responsibilities:
  • Analyze and understand existing ASIC/SoC RTL implementations, design structures, and digital logic.
  • Perform RTL analysis to identify module functionality, design intent, and architectural behavior.
  • Trace control and data paths across complex RTL hierarchies.
  • Analyze FSMs, registers, interfaces, and logic dependencies.
  • Document design behavior, architectural findings, and RTL dependencies.
  • Support design reconstruction, functional interpretation, or equivalent RTL implementation where required by the project.
  • Collaborate with design, verification, and architecture teams to resolve technical questions.
  • Review design functionality using simulation, waveform analysis, and relevant RTL analysis tools.
  • Identify design issues, ambiguities, and functional discrepancies during the analysis process.
  • Maintain clear technical documentation throughout the project.
Required Qualifications:
  • 10+ years of experience in ASIC/SoC RTL design or a closely related digital design discipline.
  • Strong hands-on experience with Verilog and SystemVerilog RTL.
  • In-depth understanding of digital logic design, RTL coding, and microarchitecture.
  • Experience analyzing complex RTL codebases and understanding existing design behavior.
  • Strong knowledge of FSMs, datapaths, control logic, registers, and digital interfaces.
  • Experience with RTL simulation, debugging, and waveform analysis.
  • Ability to work independently on technically complex design analysis tasks.
  • Strong problem-solving, documentation, and communication skills.
  • Willingness and ability to work on-site in San Diego for approximately 2 3 months.

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