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Physical Design Engineer (Synthesis, STA & Floorplanning)

SVK Technology SolutionsCA🇺🇸United StatesPosted 18 Aug 2026

Why This Role Stands Out

This role offers a fantastic opportunity to hone your skills in advanced physical design with a leading company, driving impactful projects in cutting-edge semiconductor technology. You'll thrive here if you have strong expertise in RTL synthesis, STA, and floorplanning using Cadence tools, and are eager to contribute to a dynamic, execution-driven team in the Bay Area. Apply now to advance your career in a challenging and rewarding environment!

Quick Overview

Work Type
On Site
Level
Mid Senior

Job Description

Fulltime

Location: Bay Area

Visa - Stamped H1B, s.

Note: Stamped H1B engineers, who are currently in India and are willing to join us immediately can also be considered.

Job Description Physical Design Engineer (Synthesis, STA & Floorplanning)

Strong experience in RTL synthesis using Cadence Genus, including SDC constraint development and QoR optimization (timing, area, power)

Hands-on expertise in Static Timing Analysis using Cadence Tempus, including setup/hold closure, MMMC scenarios, OCV, and timing signoff concepts

Ability to analyze and debug timing violations across synthesis and floorplan stages and drive closure

Experience in block-level floor planning using Cadence Innovus including macro placement, IO planning, utilization,

Experience in advanced nodes (5nm or below) with ability to work in a fast-paced, execution-driven environment (onsite 5 days/week mandatory)

Etched is a Cadence tool customer. The candidate must have Cadence tool (P&R, STA, Synthesis experience)

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