Senior ASIC/SoC RTL Design Engineer – RTL Design Analysis

• 10+ years of experience in ASIC/SoC RTL design or a closely related digital design discipline.
• Strong hands-on experience with Verilog and SystemVerilog RTL.
• In-depth understanding of digital logic design, RTL coding, and microarchitecture.
• Experience analyzing complex RTL codebases and understanding existing design behavior.
• Strong knowledge of FSMs, datapaths, control logic, registers, and digital interfaces.
• Experience with RTL simulation, debugging, and waveform analysis.
• Ability to work independently on technically complex design analysis tasks.
• Strong problem-solving, documentation, and communication skills.
• Willingness and ability to work on-site in San Diego for approximately 2–3 months.

Ideal Candidate Profile

The ideal candidate is a senior RTL engineer with deep digital design expertise who can quickly understand complex ASIC/SoC implementations, independently analyze existing RTL, document design behavior, and support the project team during a short-term on-site assignment.