Physical Design Engineer

• RTL Synthesis, Constraint writing, validation, Static timing Analysis
• Writing Scripts/Modiying scripts for RTL synthesis, SDC creation, STA
• Debug synthesis issues and STA
• Generate clean netlist.

What we are looking for:

• Experience: 5+ years of hands-on RTL Synthesis
• EDA exposure: Design compiler, PrimeTime, Tempus, Genus,
• Multi-Node Design: Experience working with 16nm, 7nm etc nodes.

• Bachelor s Degree in electronic engineering, or the equivalent qualification in training and experience