Senior DFX RTL Verification Engineer – Visa/JTAG/Debug Validation

Job Title: Senior DFX RTL Verification Engineer
Location: Santa Clara, CA
Experience: 8–10 Years
Job Type: Contract - 12 Months + ext 

Job Description

We are looking for a Senior DFX RTL Verification Engineer with strong experience in DFX/DFT verification, Visa, JTAG, and Debug Validation for an exciting opportunity in Santa Clara, CA.

The ideal candidate will have hands-on experience in RTL verification of DFX/debug features, developing verification environments, creating test scenarios, debugging failures, and validating JTAG/debug functionality in ASIC/SoC environments.

Required Skills

• 8–10 years of experience in RTL Design Verification
• Strong experience with DFX (Design for X) / DFT verification
• Hands-on experience with Visa / VISA Debug validation
• Strong experience with JTAG / IEEE 1149.x
• Experience in Debug Validation / Debug Logic Verification
• Strong SystemVerilog and UVM experience
• Experience developing testbenches, test cases, assertions, and functional coverage
• Strong RTL simulation and debug experience
• Experience with ASIC/SoC verification
• Knowledge of DFT, Scan, TAP Controller, and Boundary Scan
• Experience with verification/debug tools such as VCS, Verdi, Questa/ModelSim
• Strong scripting skills in Python, Perl, or Tcl preferred
• Excellent debugging and problem-solving skills

Preferred Qualifications

• Experience working on DFX/DFT RTL verification
• Experience validating JTAG, VISA, Debug, and related SoC infrastructure
• Experience with pre-silicon and/or post-silicon validation
• Experience working in a semiconductor/ASIC environment