Haystack
← Back to Jobs
Engineering

Senior Physical Design (PD) Engineer

Techridge, Inc.Sunnyvale, CA🇺🇸United StatesPosted 6 Aug 2026

Quick Overview

Work Type
Hybrid
Level
Mid Senior

Job Description

We are seeking a Senior Physical Design (PD) Engineer with 8–14 years of experience in RTL-to-GDSII implementation for advanced-node SoCs. The ideal candidate will have deep expertise in Synopsys Fusion Compiler, low-power design, timing closure, and PPA optimization on 5nm/3nm technologies.
Key Responsibilities
  • Execute complete RTL-to-GDSII physical design flow including synthesis, floorplanning, placement, CTS, routing, timing closure, and signoff.
  • Implement low-power SoC designs using UPF methodologies on advanced technology nodes.
  • Resolve SoC integration issues, SDC constraints, and UPF promotion/pushdown challenges.
  • Develop automation using Tcl, Python, and Shell scripting.
  • Optimize Power, Performance, and Area (PPA).
  • Collaborate with RTL, STA, DFT, and verification teams to achieve design closure.
  • Mentor junior engineers and contribute to flow and methodology improvements.
Required Skills
  • 8–14 years of Physical Design experience.
  • Strong expertise in Synopsys Fusion Compiler.
  • Hands-on experience with RTL-to-GDSII implementation.
  • Experience with Floorplanning, Placement, CTS, Routing, Timing Closure, and Physical Verification.
  • Expertise in UPF and Low Power Design.
  • Strong scripting skills in Tcl, Python, and Shell.
  • Experience with advanced technology nodes (5nm/3nm).
  • Excellent debugging, communication, and leadership skills.

Similar jobs

Apply now