SOC Design Verification Engineer

Immediate need for a talented SOC Design Verification Engineer. This is a 06+ Months Contract opportunity with long-term potential and is located in US (Remote). Please review the job description below and contact me ASAP if you are interested.
Job ID: 26-30161
Pay Range: $75 - $85/hour. Employee benefits include, but are not limited to, health insurance (medical, dental, vision), 401(k) plan, and paid sick leave (depending on work location).
Key Responsibilities:

• Responsible for SoC level verification, driving verification execution, integration, coverage closure, low-power verification, GLS, and test-chip validation activities.
• Develop and execute SoC-level verification plans, testcases, and coverage models to validate subsystem interactions, system functionality, and integration requirements.
• Integrate IPs, UVCs, and VIPs into the SoC verification environment.
• Drive functional/code coverage closure, power-aware verification, and Gate-Level Simulations (GLS).
• Perform debug of RTL, integration, protocol issues.
• RAL Modeling and verification.
• Own test-chip verification and collaborate with Design, DFT, Firmware, and Architecture teams for verification signoff.

Key Requirements and Technology Experience:

• Strong expertise in SystemVerilog, UVM, and SoC verification methodologies.
• Experience in testbench bring-up, SoC integration, and coverage-driven verification.
• Hands-on experience in RAL modeling and RAL-based register verification, including register access, mirroring, prediction, and functional coverage.
• Hands-on experience with UPF-based low-power verification and GLS debugging.
• Knowledge of JTAG, DAC, and analog/mixed-signal model verification.
• Strong debugging, automation, and stakeholder management skills.

Our client is a leading IT Industry and we are currently interviewing to fill this and other similar contract positions. If you are interested in this position, please apply online for immediate consideration.
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