Senior RTL Design Engineer Networking ASIC / SystemVerilog / Ethernet San Diego

Job Title: Physical Design Engineer (STA / CTS / Floorplanning)

Location: San Jose, CA
Experience: 8+ Years
Employment Type: Full-Time / Contract

Job Description:
We are looking for a skilled Physical Design Engineer with strong experience in advanced node physical implementation. The candidate will work on RTL to GDSII implementation, timing closure, and physical verification for complex semiconductor designs.

Key Responsibilities:
• Physical design implementation including Floorplanning, Placement, Clock Tree Synthesis (CTS), and Routing
• Perform Static Timing Analysis (STA) and timing closure for advanced technology nodes (28nm and below)
• Work on power grid design and clock tree optimization
• Handle signal integrity issues such as OCV/AOCV and statistical timing
• Perform IR drop analysis and power integrity verification
• Participate in physical verification and low power verification activities
• Support EDA tool benchmarking and design flow improvements
• Collaborate with RTL, verification, and CAD teams

Required Skills:
• 8+ years of experience in Physical Design implementation
• Strong knowledge of Floorplanning, Placement, CTS, and Timing Closure
• Experience with Static Timing Analysis (STA) methodologies
• Understanding of power optimization and signal integrity concepts
• Knowledge of IR drop analysis and physical verification flows
• Strong scripting skills in Tcl, Perl, or C

Preferred Skills:
• Experience in advanced technology nodes (28nm or below)
• Knowledge of Conformal Low Power (CLP) and formal verification
• Experience with industry EDA tools such as Synopsys ICC2, PrimeTime, Cadence Innovus, or Tempus

Soft Skills:
• Strong analytical and problem-solving skills
• Good communication and teamwork abilities
• Ability to work in fast-paced semiconductor design environments

How to Apply:
Interested candidates can apply through Dice or send their updated resume via LinkedIn message.