ASIC Verification Engineer – Verification Engineer 3

Location: Santa Clara, CA 95054
Contract: 12+ Months
Candidate Pay: $75/HR on W2

Job Overview

We are seeking an experienced ASIC Verification Engineer – Verification Engineer 3 to join our semiconductor engineering team in Santa Clara, CA. The ideal candidate will have strong hands-on experience in block-level functional verification of complex CPU/GPU SoCs, with expertise in simulation, SystemVerilog, Verilog, and C/C++ development in a Linux environment.

The engineer will be responsible for developing and executing verification strategies, creating test environments, and validating complex ASIC designs using both directed and constrained-random simulation methodologies.

Key Responsibilities

• Lead block-level functional verification for complex CPU/GPU SoC designs.
• Develop and execute comprehensive verification plans, test strategies, and test cases.
• Perform directed and constrained-random simulation to identify functional and design issues.
• Develop, enhance, and maintain verification environments using Verilog/SystemVerilog.
• Write and debug verification code using C/C++ in a Linux environment.
• Apply object-oriented programming (OOP) concepts and STL in verification development.
• Analyze simulation results, debug failures, and work closely with RTL/design engineers to resolve issues.
• Develop functional coverage and contribute to improving verification quality and coverage.
• Participate in design reviews, verification planning, and technical discussions.
• Support regression testing and troubleshoot complex verification failures.
• Where applicable, apply formal verification methodologies to improve design validation and coverage.

Required Qualifications

• 5–7+ years of experience in ASIC/SoC verification or related semiconductor engineering.
• Strong hands-on experience with block-level functional verification.
• Experience verifying complex CPU/GPU or SoC designs.
• Expert-level proficiency in C/C++.
• Strong Linux development and debugging experience.
• Strong knowledge of Object-Oriented Programming (OOP) and C++ STL.
• Strong expertise in Verilog and SystemVerilog.
• Experience with directed and constrained-random simulation.
• Strong debugging and problem-solving skills.
• Ability to work closely with RTL, design, architecture, and verification teams.

Preferred Qualifications

• 7+ years of ASIC/SoC verification experience preferred.
• Strong experience with Formal Verification methodologies.
• Experience with complex CPU/GPU architectures and SoC-level verification.
• Experience developing reusable verification components and infrastructure.
• Familiarity with functional coverage, regression environments, and verification automation.