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Design Verification Engineer (GPU)

Xoriant CorporationSan Jose, CA🇺🇸United StatesPosted 7 Jul 2026

Why This Role Stands Out

This role offers a fantastic opportunity to contribute to cutting-edge GPU architecture, developing your expertise in advanced verification methodologies. You'll thrive here if you're a creative and versatile engineer with a strong background in System Verilog and UVM, eager to tackle complex challenges and ensure top-tier product quality. Apply now to join a dynamic team and make a significant impact!

Quick Overview

Work Type
On Site
Level
Mid Senior

Job Description

Job Title: "Design Verification Engineer (GPU)"

Location: San Jose, CA (Onsite, 5 days a week)

Duration: Long Term

Description

As a GPU Design Verification Engineer, your talents will ensure the quality at the heart of our GPU architecture. Creativity is a necessity to overcome the challenges inherent to verifying the proper operation of our low-power GPU. Versatility and broad knowledge of state-of-the-art verification techniques including the most up-to-date IEEE UVM version will place you among the elite within our profession.

Role and Responsibilities: Key responsibilities include

  • Work with architects and designers to build verification environments and test plans
  • Craft functional verification coverage strategy to ensure complete test suite implementation
  • Develop assertions and checks to optimize isolation time and produce meaningful failing signatures
  • Analyze failing tests to root cause along, working with RTL and reference modeling teams
  • Provide input on Architectural and Micro-Architectural specifications for testability and accuracy
  • Examine code coverage results, identifying exclusions and improving stimulus
  • Take ownership of key milestone closure by meeting phase gate pass rates, coverage quality, and other quality metrics

Skills and Qualifications: Minimum requirements:

  • BS in Computer Engineering, BSEE or comparable and 5+ years of industry experience in a design verification role
  • Proficient in System Verilog/UVM/OVM, and OOP/C++
  • Deep understanding of constrained randomization and the development of efficient test suites
  • Experience with code coverage and functional coverage-driven verification methodology.
  • Experience in creating, running and debugging of SystemVerilog/UVM constraint-random testbench.
  • Working knowledge of scripting languages such as Python or Perl
  • Understanding of micro-architecture, logic design, FSMs, arithmetic datapath pipelines

Preferred qualifications:

  • MS CE/EE with 5+ years of industry experience in verification
  • Good verbal and written communication skills
  • Experience of GPU or CPU is a plus

Skills

Verilog

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