FPGA Engineer

FPGA Engineer<br />Up to £90k DOE + bonus, healthcare, enhanced pesnion, etc.<br />Cambridge (Hybrid) | 3-4 days on site Our client is looking for an FPGA Engineer to strengthen their permanent team based out of Cambridge. You'll take ownership of FPGA logic for the controller boards that sit at the heart of the company's hardware, from design through to verification and ongoing maintenance. The work is VHDL-based, targeting Xilinx Artix-7 parts in Vivado, and spans state machine design, low-level driver work (I²C, SPI), test bench development and hands-on hardware testing. Note that this sits at the discrete-logic and embedded-interfaces level rather than SoC development.

What you'll be doing:

Writing and implementing VHDL for Xilinx Artix-7 FPGAs in Vivado, following coding standards and taking part in design reviews.<br />Designing clean, deterministic state machines to sequence and control hardware interfaces.<br />Building driver logic for serial interfaces such as I²C and SPI (UART a plus) - handling initialisation, transactions and error/edge cases.<br />Developing self-checking test benches, running simulations, and documenting the verification process.<br />Bringing boards up in the lab and validating them with logic analysers and oscilloscopes, debugging as issues arise.<br />Handling timing constraints (XDC), clocking, resets and CDC analysis through to timing closure and bitstream generation.<br />Feeding into requirements gathering, module-level specs and design reviews, and supporting integration with the wider system.<br />Keeping configuration under version control (SVN) and writing up documentation - specs, interface descriptions, test plans, release notes.What we're looking for: Solid, proven VHDL experience on Xilinx devices, and comfortable across the full Vivado flow - constraints, synthesis, place &amp; route, timing closure, bitstream generation.<br />Hands-on experience with serial protocols (I²C, SPI, ideally UART too), including the trickier bus arbitration, timing and edge-case scenarios.<br />Ability to write self-checking test benches and run simulations (Vivado simulator or similar).<br />Comfortable in the lab - bringing up boards, using scopes/logic analysers, and chasing down timing or constraint issues.<br />Good grasp of CDC, metastability, reset strategy and synchronous design principles more broadly.<br />A strong documenter and communicator who's equally happy working solo or as part of a cross-functional teamUnfortunately sponsorship is not available for this role. Keen to express your interest, or find out more?<br />Option 1: Click the apply button (don’t worry, we’ll discuss your CV before submitting)<br />Option 2: Drop me a message on LinkedIn (Rachel Bush – SoCode Recruitment)