Director of Buffer & Memory Subsystem Architecture

Job Title: Director of Buffer & Memory Subsystem Architecture
Office Location: San Jose, CA
Job Type: Full-Time
Work Model: Onsite

Job Summary:

As the founding technical lead, this expert will spearhead the HW/SW co-design of next-generation HBF–xPU systems, translating complex AI workload traces into precise architectural policies for caching, prefetching, and data movement. The role demands deep hands-on expertise in memory controllers and performance modeling to define interface contracts and optimize system-level efficiency across the hardware and software stack.

Responsibilities:

• Serve as the founding technical lead of the HBF R&D team, owning HW/SW architecture decisions and technical alignment with headquarters and external partners.
• Lead HW/SW co-design by defining architecture, functional partitioning, and interface contracts across the HBF hardware and software stack.
• Drive HBF system optimization through memory architecture, performance modeling, and system-level implementation.
• Develop HBF system models and event-/trace-driven simulators for AI memory performance analysis.
• Analyze workload performance and optimize latency, bandwidth, and memory efficiency through architecture modeling.
• Validate architectural assumptions and provide data-driven insights for cross-functional architecture decisions.
• Define HBF Memory Architecture and Policies.

Qualifications:

• 8+ years of experience in Memory Controllers, Cache/Prefetch architectures, SSD/Storage Controllers, Accelerator Memory systems, and DMA/Data Movement architectures, including the development of queueing, scheduling, and buffer management algorithms.
• Strong expertise in system performance analysis, including memory latency, bandwidth, locality, contention, and Workload characterization, with the ability to translate complex workload traces into architectural policies.
• Proven HW/SW co-design experience, including the ability to translate AI workload, compiler, runtime, and inference-engine behavior into memory hierarchy, data-movement, prefetch, scheduling, and programming-model requirements.
• Experience owning system architecture decisions, technical requirements, interface definitions, and performance acceptance criteria across multiple hardware and software components.
• Experience defining functional partitioning and interface contracts across hardware, firmware, drivers, compiler/runtime, and application software.
• Experience developing or extending simulation tools for architectural modeling using Python, C/C++, SystemC, or comparable modeling environments, including event-driven, trace-driven, or queueing-based models.

Benefits:

• Top Tier health insurance at no employee cost
• Paid day offs: Paid Time Off, Company Holidays, Parental Leave, Happy Fridays
• 401k Matching
• Flexible Spending Account (FSA) for Health Care & Dependent Care
• Educational reimbursement up to $10,000 per year
• Donation Matching and volunteering opportunities
• Corporate discount programs
• Free Breakfast/Lunch/Dinner provided to employees