Senior Staff / Principal Engineer – SerDes Analog/Mixed-Signal Design

About the Role

Upscale AI is building advanced SerDes technology to address the rapidly increasing bandwidth and energy-efficiency demands of AI data centers. We are seeking experienced analog and mixed-signal design engineers to lead the development of critical circuit blocks and contribute to the design of next-generation high-speed connectivity solutions.

Responsibilities:

• Own the design and development of complex analog/mixed-signal circuits for high-speed SerDes and foundation IP.

• Translate system-level specifications into circuit architectures, design strategies, and measurable implementation targets.

• Evaluate architectural alternatives and optimize performance, power, area, noise, linearity, bandwidth, and robustness as applicable.

• Lead transistor-level design, behavioral modeling, simulation, verification, and post-layout performance closure.

• Drive technical reviews, communicate design trade-offs, and provide technical guidance to other engineers.

• Support silicon bring-up, characterization, correlation against simulations, and root-cause analysis of performance issues.

Qualifications:

• M.S. or Ph.D. in Electrical Engineering or a related field.

• Significant industry experience in analog/mixed-signal IC design, 100G+ high-speed circuit design, or related semiconductor development.

• Demonstrated expertise in transistor-level circuit design, simulation, and performance optimization.

• Experience taking complex circuit blocks through implementation, verification, and design closure.

• Strong understanding of circuit-level trade-offs and the ability to connect circuit performance to system-level requirements.

• Proficiency with industry-standard circuit simulators and design tools.

• Strong technical communication, problem-solving, and cross-functional collaboration skills.

Preferred Qualifications:

• Proven experience in 100G+ high-speed SerDes or other demanding analog/mixed-signal IC development.

• Experience in advanced-node CMOS technologies and associated challenges in parasitics, variability, power, and signal integrity.

• Proven success in one or more of the following technical areas:

• Fractional-N PLL, LC-VCO, DTC/TDC, multi-modulus divider (MMD).

• Phase interpolator, injection-locked oscillator, multi-phase clock generator.

• High-speed time-interleaved DAC and line driver.

• Transimpedance amplifier, CTLE, PGA, Cherry-Hooper amplifier, high-speed voltage followers.

• Time-interleaved SAR ADC, track-and-hold circuits.

• Bandgap, PTAT, LDO, temperature sensor, charge pump, auto-zero comparator, R2R DAC.

• Experience with post-layout analysis, silicon characterization, and silicon-to-simulation correlation.

• Track record of independently driving complex technical tasks to successful completion.

• Experience mentoring engineers, reviewing designs, and establishing effective design practices.

• Familiarity with Python, MATLAB, or other tools for modeling, automation, and optimization.

We are looking for engineers who combine strong circuit-design fundamentals with independent technical judgment and a track record of delivering robust silicon.