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Design For Test (DFT) Engineer

West Coast Consulting LLCSan Jose, CA🇺🇸United StatesPosted Oct 13, 2026

Why This Role Stands Out

You'll gain invaluable experience validating next-generation Samsung chips, directly impacting cutting-edge RF and wireless technologies, and this on-site role offers a fantastic opportunity for independent problem-solving and skill development. If you have 5+ years of DFT experience and a passion for complex silicon challenges, you're exactly who they're looking for to contribute to this innovative team. Apply today to take your career to the next level!

Quick Overview

Seniority
Mid Senior
Work mode
On Site
Location
San Jose, CA, United States
Posted
4 days ago
Verilog

Job Description

Job Description
Onsite San Jose - 5 days a week
Description
The team is looking for a Design-for-Test contractor to test and validate the next generation Samsung chips.
Candidate will be responsible to work with Front End and Physical Design teams to implement DFT and test designs which will impact the product lines for radio frequency (RF) and BlueTooth/Wireless LAN chipsets.

JOB RESPONSIBILITIES

Experience with memory BIST - Siemens Tessent Flow
Experience with gate-level simulation and simulation debug
Experience with automation and scripting - Tcl/Perl/Python
Experience with scan compression - SEQ/Ultra/TestKompress
Experience with ATPG - Tetramax
Experience with ATPG diagnosis, ATE debug and silicon bring up
DFT pattern translation - VTRAN
Experience with RTL design - Verilog/system Verilog
Some experience with STA and timing analysis concepts - PrimeTime (CDC, clock gating checks, timing constraints)
REQUIRED SKILLS AND EXPERIENCE:
5+ years relevant industrial DFT experience
Excellent problem solving and debugging skills
Ability to complete assignments independently

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