Physical Design Engineer - W2 Position

Position : Physical Design Engineer

Location : Palo Alto, CA

Number of Positions : 5

JD for PD:

• Exposure to TSMC 2NP/3NP is must
• Perform endtoend physical design flow:
• Floorplanning
• Power planning (PG grid, IR)
• Placement & optimization
• CTS (Clock Tree Synthesis)
• Routing
• Postroute optimization
• Achieve timing closure across all modes and corners
• Resolve DRC, LVS, ERC and signoff violations
• Handle lowpower design techniques:
• MultiVt, Multivoltage (UPF)
• Power gating, clock gating
• Perform physical verification and signoff:
• STA (Primetime)
• SI / Crosstalk
• IR drop & EM analysis
• Work on advanced nodes (7nm, 5nm, 3nm or below)
• Collaborate with:
• RTL & Microarchitecture teams
• DFT & Test engineers
• Foundry and CAD teams
• Debug complex timing, congestion, power, and variability issues
• Drive methodology improvements and automation (scripts/flows)