Why this role stands out
This hybrid role at Metalight Solutions Inc. offers significant growth potential, allowing you to hone your skills in advanced semiconductor nodes and end-to-end physical design flows. You'll thrive here if you're a mid-senior engineer eager to collaborate with diverse teams and drive innovation in a reputable company. Apply now to shape the future of cutting-edge technology!
Quick overview
Job description
JD for PD:
- Exposure to TSMC 2NP/3NP is must
- Perform endtoend physical design flow:
- Floorplanning
- Power planning (PG grid, IR)
- Placement & optimization
- CTS (Clock Tree Synthesis)
- Routing
- Postroute optimization
- Achieve timing closure across all modes and corners
- Resolve DRC, LVS, ERC and signoff violations
- Handle lowpower design techniques:
- MultiVt, Multivoltage (UPF)
- Power gating, clock gating
- Perform physical verification and signoff:
- STA (Primetime)
- SI / Crosstalk
- IR drop & EM analysis
- Work on advanced nodes (7nm, 5nm, 3nm or below)
- Collaborate with:
- RTL & Microarchitecture teams
- DFT & Test engineers
- Foundry and CAD teams
- Debug complex timing, congestion, power, and variability issues
Drive methodology improvements and automation (scripts/flows)
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