SR PHYSICAL DESIGN ENGINEER _ FULL TIME

TITLE: SR PHYSICAL DESIGN ENIGNEER

LOCATION: SUNNYVALE, CA (ONSITE)

FULL TIME ROLE

Senior ASIC/SoC Physical Design Engineer with 10+ years of experience who has strong hands-on expertise in RTL synthesis, optimization, and floor planning. The candidate should be capable of optimizing chip designs for Power, Performance, and Area (PPA), improving timing and congestion, analyzing netlists, and supporting timing closure. Must have experience working closely with RTL design, verification, and physical design teams to deliver high-quality ASIC/SoC implementations.

Mandatory Skills:

• 10+ years of ASIC/SoC Physical Design experience.

• RTL Synthesis and Optimization.

• Floor Planning (advanced technology nodes).

• Timing Optimization and Timing Closure.

• Netlist Optimization.

• PPA Optimization (Power, Performance, Area).

• Physical Implementation methodologies.

• EDA Synthesis and Physical Design tools.

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  EMAIL (:) NAVEEN AT SUNRAYINFORMATICS DOT COM