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Principal Digital Hardware Design Engineer

Everpure, Inc.Santa Clara, CA🇺🇸United StatesPosted Oct 5, 2026

Why This Role Stands Out

As a Principal Digital Hardware Design Engineer at Everpure, Inc., you will lead the architecture and validation of cutting-edge enterprise storage hardware, directly impacting the next era of AI and data platforms. This role is ideal for a seasoned engineer who thrives on technical leadership, cross-functional collaboration, and driving innovation within a rapidly growing, reputable company. You'll have the opportunity to shape critical technology and contribute to world-changing advancements.

Quick Overview

Seniority
Leader
Work mode
On Site
Location
Santa Clara, CA, United States
Posted
5 hours ago
PCB DesignVerilog

Job Description

P) has evolved from storage pioneer to data platform, closing fiscal 2026 with $3.7 billion in revenue, its first billion-dollar quarter, and accelerating growth into FY27. Our strategic agenda spans the companies defining the next era of technology - hyperscalers, AI labs, the AI hardware supply chain, data platform providers, and the broader AI ecosystem. This type of work—work that changes the world—is what the tech industry was founded on.

As a key contributor on our System Hardware Development team, you will drive the end-to-end architecture, validation, and quality of enterprise-class storage hardware systems that power mission-critical data environments. You will bridge complex engineering concepts with real-world deployment by leading cross-functional alignment across internal engineering, Joint Development Manufacturing (JDM) partners, operations, and support teams.

In this role, your technical leadership ensures unmatched system reliability, performance, and scalability across our next-generation storage portfolio while establishing design methodologies that accelerate product innovation. Drive Next-Generation Hardware Architecture & Design : Lead schematic capture, high-speed PCB layout, signal integrity analysis, and x86 system-level co-development alongside JDM partners to deliver scalable, high-performance enterprise storage platforms from concept through production.

Architect Comprehensive Qualification & Automation Frameworks : Oversee functional specifications and automated stress testing environments—leveraging Linux, Python, PCIe, DDR, Ethernet, and serial bus protocols—to guarantee sub-system reliability and accelerate time-to-market. Champion Cross-Functional Hardware Operations & System Hardening : Partner with Manufacturing, Operations, and Escalation teams to streamline production handoffs for new storage sub-systems and perform deep root-cause failure analysis that permanently hardens enterprise products.

Establish Quality-by-Design Standards & Best Practices : Define hardware validation methodologies, collaborate across organizational boundaries, and build engineering networks that continuously elevate quality benchmarks across all product development lifecycles. Expertise in x86 system architecture, high-speed PCB design layout, signal integrity analysis, schematic capture, and major bus technologies (PCIe, DDR, Ethernet, I2C, SPI) to independently validate enterprise hardware at electrical, protocol, and functional levels.

Advanced System Testing & Automation : Ability to design and automate system-level stress tests (using Linux environments, Python/BASH scripting, PTU, LinPack, and IOmeter) and utilize high-speed oscilloscopes and bus analyzers to perform complex signal and protocol trace analysis. Capability to lead root-cause failure analysis on complex technical issues, establish engineering best practices, and collaborate effectively with internal teams and external manufacturing partners to deliver production-ready systems.

Solid understanding of Verilog and CPLD design concepts combined with a rigorous, quality-focused mindset for hardware design and system-level troubleshooting. We are primarily an in-office environment and therefore, you will be expected to work from the Santa Clara, CA office in compliance with Everpure’s policies, unless you are on PTO, or work travel, or other approved leave.
#This role may be eligible for incentive pay and/or equity. There is no application deadline and we accept applications on an ongoing basis until the job is filled.

And because we understand the value of bringing your full and best self to work, we offer a variety of perks to manage a healthy balance, including flexible time off, wellness resources, and company-sponsored team events. Candidates with disabilities may request accommodations for all aspects of our hiring process. That’s why we are committed to fostering the growth and development of every person, cultivating a sense of community through our Employee Resource Groups and advocating for inclusive leadership.

We do not discriminate based upon race, religion, color, national origin, sex (including pregnancy, childbirth, or related medical conditions), sexual orientation, gender, gender identity, gender expression, transgender status, sexual stereotypes, age, status as a protected veteran, status as an individual with a disability, or any other characteristic legally protected by the laws of the jurisdiction in which you are being considered for hire.

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