Design Verification Engineer

Hi,

Role : Design Verification Engineer Location: San Jose, CA - Onsite

Hands-on experience with industry-standard verification methodologies like System Verilog/UVM and understand how to build scalable, reusable testbenches.

• Experience handling vendors and integration of IP/VIP s
• UVM/System Verilog
  
  

  Thanks and Regards,

  Praveenkumar