DFT Engineer

Job Title: DFT Engineer
Number of Positions: 9
Location: Santa Clara, CA
Client: NVIDIA
Experience: 5+ Years
Work Arrangement: As per Client Requirement

Job Summary

5+ years of hands-on experience in DFT and ATPG for SoC or ASIC designs Strong understanding of DFT fundamentals including controllability, observability, and scan-based testing Proven expertise in ATPG pattern generation, analysis, and debug Experience with MBIST, including memory test architectures and diagnostics Knowledge of IO Test methodologies for interface and pin level validation Solid understanding of clock DFT and clock verification concepts Strong grasp of digital design and RTL fundamentals Experience with industry standard DFT/ATPG EDA tools Ability to work effectively in fast paced, high performance semiconductor programs Strong analytical, problem solving, and communication skills