Lead ASIC Verification Engineer

Title: Lead Verification Engineer
Duration: 24 month contract + possible extension
Locations Available: Boise, ID, Salt Lake City, UT, Scottsdale, AZ or San Jose, CA - Hybrid - 2x on site and 3x remote
Pay Rate Range: $75-85/hr. W2
Clearance: Active Secret Clearance Required

Responsibilities:
Bachelor's degree in Electrical or Computer Engineering, or a related Science, Engineering or Mathematics field, plus a minimum of 10 years of relevant experience; or Master's degree plus a minimum of 8 years of relevant experience.
Qualifications:
As a Lead ASIC verification engineer you’ll support a cross functional team responsible for designing and architecting advanced embedded security technologies that protect U.S. defense systems from cyber exploitation, physical attacks, reverse engineering, and supply chain compromise.

Employees deliver secure processors, anti tamper architectures, cryptographic IP, and integrated firmware/software solutions designed to meet stringent government cybersecurity and survivability requirements. anti-tamper and physical HW security produts.
Duties and Tasks
• Leads ASIC verification at the block, subsystem, and full-chip levels.
• Develops verification plans, schedules, coverage goals, and completion criteria.
• Builds reusable SystemVerilog/UVM test environments and verification components.
• Maintains traceability from requirements through test results and defect closure.
• Plans and executes simulation, regression, formal verification, and emulation activities.
• Drives coverage and regression results to predetermined completion goals.
• Leads failure investigation, root-cause analysis, and corrective-action verification.
• Verifies third-party and custom IP for functional and integration compliance.
• Provides feedback to design and architecture teams on issues that affect verification.
• Identifies verification risks and develops practical mitigation plans.
• Presents verification status, evidence, risks, and recommendations at technical reviews.
• Produces clear, accurate verification plans, procedures, and reports.
• Improves verification processes, automation, metrics, and reusable assets.
• Provides technical direction and mentoring to verification engineers.
• Supports vendor oversight, proposals, estimates, and program planning as needed.
• Uses approved AI-enabled tools where they provide clear engineering value and protect sensitive information.
Required Knowledge, Skills, and Abilities
• Strong knowledge of ASIC and SoC verification processes.
• Strong proficiency in SystemVerilog, UVM, assertions, coverage, and regression testing.
• Experience developing reusable testbench components and register models.
• Strong understanding of RTL, digital logic, interfaces, clocks, and resets.
• Ability to convert requirements into measurable verification objectives and tests.
• Experience debugging simulations and determining root causes.
• Experience with scripting languages such as Perl, Tcl, Bash, and Python.
• Experience with ASIC simulation and debug tools such as VCS, Verdi, Questa, or equivalent tools.
• Experience with Linux, version control, and automated regression environments.
• Ability to communicate technical results clearly to varied audiences.
• Ability to lead multiple activities while maintaining quality and schedule.
• Strong technical judgment, mentoring, and problem-solving skills.
Preferred Qualifications
• Experience with formal verification, CDC/RDC analysis, or low-power verification.
• Experience with emulation, silicon bring-up, or post-silicon validation.
• Experience verifying third-party IP and complex interfaces.
• Experience working in an Agile development environment.
• Experience with vendor oversight, proposals, estimates, or program controls.
Expected Performance Outcomes
Successful performance in this role is demonstrated by:
• Verification plans and requirements traceability are complete and current.
• Results provide credible evidence that design requirements are met.
• Coverage, regression, and defect goals are achieved or have approved exceptions.
• Critical failures and risks are identified early and resolved on schedule.
• Technical reviews receive clear, accurate, and timely information.
• Verification methods and automation improve program execution over time.
• Technical leadership supports successful completion of program milestones.