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Technical Lead – Marvell ASIC / CPSS / SAI / C++ / Datapath

EL-Shaddai Technologies IncSan Jose, CA🇺🇸United StatesPosted 8 Sept 2026

Quick Overview

Seniority
Mid Senior
Work mode
Hybrid
Location
San Jose, CA, United States
Posted
18 hours ago
MicroservicesACLSLoad BalancingC++

Job Description

Technical Lead (TL) – Platform
Development (Marvell Silicon / Forwarding Layer)


Location: San Jose

Experience Level: 10+ Years

Role Overview

As a Technical Lead for Platform
Development focusing on Marvell Silicon, you will lead the forwarding
plane development and driver/SDK integration for ArcOS. You will architect
high-density forwarding pipelines optimized for AI clusters, data center
leaf/spine fabrics, and next-generation service provider infrastructure.


Key Responsibilities

  • Data Path Engineering: Architect

and write microservices-based forwarding drivers that map abstract
routing/switching instructions into Marvell switch ASIC pipelines.

  • Marvell SDK / API Integration:

Integrate Marvell SDKs (CPSS, SAI, or Teralynx SDKs) to manage ASIC
lookups, ACLs, forwarding tables, and link management.

  • AI & Telemetry Optimization:

Implement hardware-assisted traffic management features such as telemetry
(INT), telemetry-driven load balancing, and congestion notification for
high-density AI fabric environments.

  • Kernel & User-space Abstraction: Maintain and enhance ArcOS’s Data Plane Adaptation Layer

(DPAL) for seamless portability to Marvell silicon variants.

  • Cross-Functional Execution:

Collaborate with control plane, system test, and product management teams
to deliver carrier-grade stability and line-rate performance.


Technical Requirements

  • 10+ years of software engineering

experience in datapath forwarding, hardware platform development, and
vendor SDK integration.

  • Marvell Chipset Expertise:

Extensive experience programming and debugging Marvell switch silicon:

  • Marvell Prestera / Falcon / AC5x Family: Deep familiarity with Marvell CPSS (Core Packet Software

Suite) or SAI abstractions.

  • Innovium / Teralynx (if applicable): Experience programming low-latency Teralynx pipelines for

hyperscale and AI data center fabrics.

  • Systems & Low-Level C/C++:

Mastery of C and C++ programming for hardware-level, thread-safe,
multi-core system environments.

  • Forwarding Domain Mastery: Comprehensive

expertise in packet parsing pipelines, exact-match and LPM lookups, ACLs,
telemetry (In-band Network Telemetry/INT), and buffer management.

  • Networking Infrastructure: Strong

knowledge of L2/L3 protocols (BGP-EVPN, VXLAN, MPLS, Segment Routing/SRv6)
and how control plane states map to hardware tables.

  • Linux Platform Software: Solid

foundation in Linux kernel drivers, user-space networking (DPDK/SAI), PCIe
access, and memory-mapped I/O (MMIO).

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