Senior Emulation Engineer

Role: Senior Emulation Engineer (ZeBu)

Location: Fremont, CA ( Onsite )

Duration: Fulltime

Salary range :- $180k-$200k yearly

Job Overview

We are seeking a highly skilled and motivated Senior Emulation Engineer to drive the pre-silicon validation of our next-generation processor and complex System-on-Chip (SoC) architectures. In this role, you will be responsible for emulation model compile/build flows, hardware-software co-validation, early firmware bring-up, and performance optimization predominantly using Synopsys ZeBu

emulation platforms. You will collaborate closely with RTL Design, Design Verification (DV), Architecture, and Software teams to identify critical design defects before silicon tape-out.

Key Responsibilities

• Model Build & Deployment: Deploy, compile, partition, and validate complex RTL designs on Synopsys ZeBu emulation hardware.
• Environment Development: Develop and maintain synthesizable testbenches, transactors, and emulation-specific infrastructure.
• Pre-Silicon Validation: Port and execute simulation verification test cases onto the emulation platform to validate system-level behavior and performance.
• Debug & Root-Cause Analysis: Analyze failures, logs, waveforms, and traces to debug complex hardware-software interactions and drive design defects to resolution.
• SW/FW Integration: Support software and firmware engineering teams in early boot-up, OS execution, and system-level debugging before first silicon is available.
• Automation: Build, maintain, and optimize regressions, runtime efficiency, and compile flows utilizing scripting languages.
• Collaboration: Partner with cross-functional architecture, DFT, and post-silicon teams to establish scalable pre-silicon validation methodologies.

Required Technical Skills

• Emulation Platforms: Expert hands-on experience with Synopsys ZeBu (ZeBu Server 4/5). Familiarity with alternative platforms like Cadence Palladium or Siemens Veloce is highly desirable.
• Hardware Description & Verification: Strong proficiency in Verilog, SystemVerilog, and UVM-based validation methodologies.
• Protocols & Subsystems: Deep understanding of industry-standard protocols, including AMBA (AXI/AHB/APB), PCIe/CXL, DDR/LPDDR memory interfaces, and IOMMU.
• Scripting & Automation: Strong programming skills in Python, Tcl, Perl, or Shell scripting for building automation pipelines.
• Architecture Knowledge: Familiarity with CPU (e.g., ARM, RISC-V, or x86) and GPU subsystem architectures

Qualifications & Experience

• Education: Bachelor’s or Master’s degree in Electrical Engineering, Electronics & Communication, Computer Engineering, or a related field.
• Experience: 5+ years of direct, hands-on experience in ASIC/SoC pre-silicon validation and hardware emulation.
• Soft Skills: Exceptional problem-solving capabilities, a strong team-oriented mindset, and excellent verbal and written communication skills.