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Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

Comprehensive Resources Inc.San Jose, CA🇺🇸United StatesPosted 21 Aug 2026

Why This Role Stands Out

Take the lead on cutting-edge PCIe Gen5/Gen6 verification, architecting robust UVM environments and driving strategy for a reputable company. This hybrid role is perfect for an experienced verification engineer with deep PCIe protocol expertise who thrives on technical challenges and mentorship. You'll gain invaluable experience in a dynamic environment and contribute to the success of next-generation technology.

Quick Overview

Seniority
Leader
Work mode
Hybrid
Location
San Jose, CA, United States
Posted
6 days ago

Job Description

Verification Lead / Principal Verification Engineer - PCIe Gen5/Gen6

Location: San Jose, CA

Experience: 10+ Years

Job Type: Contract / Long-Term

Job Summary

We are seeking a Verification Lead / Principal Verification Engineer with strong hands-on experience in PCIe Gen5/Gen6 verification to lead end-to-end verification of PCIe Controller and Subsystem IP.

The ideal candidate will have deep expertise in PCIe protocol, UVM, SystemVerilog, LTSSM, PIPE, PHY/SerDes, assertions, coverage closure, emulation, and protocol compliance.

Responsibilities

  • Own PCIe Gen5/Gen6 verification strategy, planning, execution, and signoff.
  • Review PCIe architecture, microarchitecture, specifications, and RTL.
  • Develop and architect reusable UVM-based verification environments.
  • Verify PCIe Transaction Layer, Data Link Layer, Physical Layer, and PIPE interfaces.
  • Develop test plans, testcases, scoreboards, assertions, and coverage models.
  • Verify LTSSM, link training, equalization, recovery, speed changes, and lane-width changes.
  • Verify Controller-to-PHY integration and PCIe protocol compliance.
  • Drive functional, code, assertion, and cross-coverage closure.
  • Support IP, subsystem, and SoC-level verification.
  • Support emulation, post-silicon debug, and silicon validation.
  • Lead and mentor verification engineers.
  • Collaborate with Architecture, RTL Design, DFT, Firmware, Physical Design, PHY, and Validation teams.

Required Skills

  • 10+ years of ASIC/SoC Design Verification experience.
  • Strong hands-on PCIe Gen5/Gen6 verification experience.
  • Deep understanding of PCIe Transaction, Data Link, and Physical Layers.
  • Strong knowledge of LTSSM, PIPE, link training, equalization, and recovery.
  • Expert-level SystemVerilog and UVM.
  • Strong SVA/assertion-based verification experience.
  • Functional, code, assertion, and cross-coverage experience.
  • PCIe Controller-to-PHY/SerDes integration experience.
  • SR-IOV and advanced PCIe features preferred.
  • Emulation experience with Veloce, Palladium, or ZeBu preferred.
  • Strong technical leadership and communication skills.

Education

Bachelor's or Master's degree in Electrical Engineering, Computer Engineering, Electronics Engineering, or related field.

To Apply: Please send your updated resume to .

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