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Principal Digital Design Engineer

Astera LabsSan Jose🇺🇸United StatesPosted 14 Sept 2026

Why This Role Stands Out

This Principal Digital Design Engineer role at Astera Labs offers a remarkable opportunity to shape the future of AI infrastructure, working with cutting-edge connectivity solutions. You'll thrive here if you possess a strong background in digital design and a passion for complex SoC development, contributing to a company at the forefront of technological innovation. Apply now to join a dynamic team and make a significant impact in the rapidly evolving AI landscape.

Quick Overview

Seniority
Leader
Location
San Jose, United States
Posted
Yesterday
ExpressPython

Job Description

Astera Labs (NASDAQ: ALAB) provides rack-scale AI infrastructure through purpose-built connectivity solutions. By collaborating with hyperscalers and ecosystem partners, Astera Labs enables organizations to unlock the full potential of modern AI. Astera Labs’ Intelligent Connectivity Platform integrates CXL®, Ethernet, NVLink, PCIe®, and UALink™ semiconductor-based technologies with the company’s COSMOS software suite to unify diverse components into cohesive, flexible systems that deliver end-to-end scale-up, and scale-out connectivity. The company’s custom connectivity solutions business complements its standards-based portfolio, enabling customers to deploy tailored architectures to meet their unique infrastructure requirements. Discover more at www.asteralabs.com.

Job Description

We are looking for Principal Digital Design Engineers with experience developing micro-architecture and implementation of the front-end circuit design, including RTL, synthesis, IP integration, and block-level verification for high performance network controllers. The candidate must have good knowledge of communication/interface protocols such as PCI-Express (Gen-3 and above), Ualink, Esun, Ethernet etc.

Basic Qualifications:

  • Strong academic and technical background in electrical engineering. A Bachelor’s degree in EE is required, and a Master’s degree is preferred.
  • +8 years’ experience supporting or developing complex SoC/silicon products for Switch ASIC, Networking applications and/or Server, Storage.
  • Professional attitude with the ability to prioritize a dynamic list of multiple tasks, plan and prepare for customer meetings in advance, and work with minimal guidance and supervision.
  • Entrepreneurial, open-mind behavior and can-do attitude. Think and act fast with the customer in mind!
  • Authorized to work in the US and start immediately.

Required Experience:

  • Hands-on, thorough knowledge of high-speed protocols like PCIe, Ualink, Esun, Ethernet, etc.
  • Proven front end design expertise – architecture, RTL, simulations, synthesis, timing closure, GLS, DFT etc.
  • Full chip or block level ownership from architecture to GDS, driving multiple complex designs to production
  • Experience with Synopsys and/or Cadence digital design tools/flows
  • Good knowledge of design for test (DFT), stuck-at and transition scan test insertion
  • Familiarity with UVM based design verification
  • Silicon bring-up and debug expertise
  • Small-geometry CMOS (≤28nm) design

Preferred Experience:

  • Firmware development with C-language, scripting with Python or other equivalent programming languages.
  • Development/support for PCIe or Ethernet Switch products.

The base salary range is $185,000.00 USD – $230,000.00 USD. Your base salary will be determined based on your location, experience, and the pay of employees in similar positions. 

 

We know that creativity and innovation happen more often when teams include diverse ideas, backgrounds, and experiences, and we actively encourage everyone with relevant experience to apply, including people of color, LGBTQ+ and non-binary people, veterans, parents, and individuals with disabilities.

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