Analog Layout Engineer

Job Title: Analog Layout Engineer (592074)

Location: San Jose, CA (Onsite)

Duration: Long Term Contract

Description

As an Analog Layout Engineer, you will be responsible for:

• Layout of Analog / High Speed transceiver circuit blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc. in a timely manner.

• Layout of sensitive active / passive components including resistors, capacitors and inductors.

• Design verification including DRC, LVS, ERC and ANT and extraction.

• Block level floor planning with design engineers.

• Review and update layout for quality including signal integrity, power integrity and parasitic.

Requirements

Associate degree or above with formal training in custom analog layout; BSEE or above preferred The ideal candidate will have the following qualifications:

• 5+ years analog layout experience in deep sub-micron and FinFET processes.

• Experience in floor planning and layout of analog blocks such as amplifiers, drivers, ADC, DAC, LDO, PLL, filters, etc.

• Solid knowledge in device structures.

• Understand tradeoffs in matching, coupling, parasitic effects, area, etc.

• Understand causes and preventions of ESD and latch-up.

• Proficient in interpreting verification DRC, LVS, ERC, ANT results.

• Working knowledge of Cadence Virtuoso and Mentor Calibre required.

• Team player with excellent communication skills.