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Live roles: 60
Added this week: 60
Countries: 15

475,055 verified tech candidates

60 jobs found

TE
DFT Engineer
New
Tenstorrent
Santa Clara🇺🇸9 hours ago
Compliance
Python
RISC-V
Engineering
TU
Machine Learning for Physical Design Intern - CPU/AI Hardware
New
Tenstorrent University Jobs
Santa Clara🇺🇸Yesterday
Machine Learning
Compliance
C++
+2
Technology
TE
Staff Business Applications Engineer, IT
New
Tenstorrent
Santa Clara🇺🇸Yesterday
Microservices
CRM
ERP
+2
Engineering
TE
Sr. Engineer, Ethernet IP
New
Tenstorrent
Santa Clara🇺🇸Yesterday
Compliance
RISC-V
Engineering
TE
PCB Layout Engineer
New
Tenstorrent
Santa Clara🇺🇸Yesterday
Compliance
Altium
PCB Design
+1
Engineering
TE
Staff, Component Engineer
New
Tenstorrent
Santa Clara🇺🇸Yesterday
Compliance
Procurement
RISC-V
+2
Engineering
TE
Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)
New
Tenstorrent
Santa Clara🇺🇸Yesterday
Compliance
Python
RISC-V
Engineering
TU
Software Engineering Intern, Power Modeling & AI Tools
New
Tenstorrent University Jobs
Santa Clara🇺🇸Yesterday
SQL
Compliance
Git
+3
Technology
TE
Staff Software Engineer, Cloud Infrastructure
New
Tenstorrent
Santa Clara🇺🇸Yesterday
AWS
Ansible
Compliance
+5
Technology
TU
Design Verification Software Intern
New
Tenstorrent University Jobs
Santa Clara🇺🇸Yesterday
FPGA
Assembly
Compliance
+5
Technology
TE
Chiplet Physical Design Engineer
New
Tenstorrent
Santa Clara🇺🇸Yesterday
Compliance
Python
RISC-V
Engineering
TE
Technical Program Manager, Product Software
New
Tenstorrent
Santa Clara🇺🇸Yesterday
Compliance
Confluence
Jira
+2
Technology
TE
RISC-V AI / HPC & Agentic Software Engineering Lead
New
Tenstorrent
Santa Clara🇺🇸Yesterday
Compliance
C++
RISC-V
Technology
TE
RISC-V Software TPM & Ops
New
Tenstorrent
Santa Clara🇺🇸Yesterday
Compliance
RISC-V
Recruiting
+1
Technology
TE
Sr. Engineer, Package Design
New
Tenstorrent
Santa Clara🇺🇸Yesterday
Compliance
Electrical Design
RISC-V
Engineering
TU
Software Intern - AI Compilers
New
Tenstorrent University Jobs
Santa Clara🇺🇸Yesterday
Machine Learning
Compliance
C++
+2
Technology
TE
Sr. Staff Engineer, RISC-V Software Workload Enablement
New
Tenstorrent
Australia; Santa Clara🇺🇸Yesterday
Compliance
RISC-V
Technology
EV
SAP Plan to Forecast Lead, SCM
New
Everpure
Santa Clara🇺🇸Yesterday
Compliance
Continuous Improvement
Demand Planning
+4
Technology
EV
Software Engineering Manager, Hyperscale Line of Business
New
Everpure
Santa Clara🇺🇸Yesterday
Compliance
Concrete
HTTP
+2
Technology
EV
Signal Integrity Hardware Engineer
New
Everpure
Santa Clara🇺🇸Yesterday
Compliance
PCB Design
HTTP
Technology

Load More Jobs

Get hired without the hassle.

DFT Engineer

Machine Learning for Physical Design Intern - CPU/AI Hardware

Staff Business Applications Engineer, IT

Sr. Engineer, Ethernet IP

PCB Layout Engineer

Staff, Component Engineer

Physical Design Engineer: Die-to-Die Interface (RTL to GDSII)

Software Engineering Intern, Power Modeling & AI Tools

Staff Software Engineer, Cloud Infrastructure

Design Verification Software Intern

Chiplet Physical Design Engineer

Technical Program Manager, Product Software

RISC-V AI / HPC & Agentic Software Engineering Lead

RISC-V Software TPM & Ops

Sr. Engineer, Package Design

Software Intern - AI Compilers

Sr. Staff Engineer, RISC-V Software Workload Enablement

SAP Plan to Forecast Lead, SCM

Software Engineering Manager, Hyperscale Line of Business

Signal Integrity Hardware Engineer

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