Hiring: DFT Lead | 7nm & Below | Saratoga, CA | Full-Time

We re looking for a seasoned DFT Leader to architect and drive test strategy for complex multi-chip SoCs at advanced nodes (7nm and below).

Own DFT architecture (Scan, LBIST, MBIST, Memory Repair, OCC, ACJTAG/DCJTAG)
Lead ATPG & achieve high @speed scan coverage
Hands-on with Synopsys or Mentor test tools
Multiple deep submicron tape-outs required
SerDes + EMIB exposure is a plus
15+ years semiconductor experience

This is a high-impact leadership role shaping next-gen high-performance silicon.

Interested? Please send me your rsume.