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Verification Lead / Principal Verification Engineer PCIe Gen5/Gen6

StoneGate-Technologies LLCSan Jose, CA🇺🇸United StatesPosted 31 Aug 2026

Why This Role Stands Out

Step into a leadership role driving cutting-edge PCIe Gen5/Gen6 verification, where you'll shape strategy and mentor a team for significant impact. This hybrid position is ideal for a seasoned verification engineer with deep PCIe expertise and a passion for architecting robust UVM environments, offering excellent opportunities for professional growth and technical mastery. Apply today to lead innovation in a dynamic engineering environment.

Quick Overview

Seniority
Leader
Work mode
Hybrid
Location
San Jose, CA, United States
Posted
Yesterday

Job Description

Position Summary
Seeking a Principal Verification Engineer to lead endtoend verification of PCIe Gen5/Gen6 subsystems, including Transaction Layer, Controller, PHY, and SerDes. This role owns verification strategy, UVM environment architecture, coverage closure, protocol compliance, and leadership of a verification team. Requires deep expertise in PCIe protocol, LTSSM, PHY/SerDes interactions, UVM, assertions, formal verification, emulation, and postsilicon debug.

Main Skills (Core Requirements)
PCIe Gen5/Gen6 protocol expertise

Transaction / Data Link / Physical Layers

LTSSM, equalization, link training, recovery

PHY / SerDes integration

UVM methodology, reusable environments

Assertions, SVA, formal verification

Functional / Code / Assertion / Cross Coverage

PIPE interface compliance

Subsystem & SoClevel verification

Verification planning & signoff

Team leadership & mentoring

Key Responsibilities
Verification Ownership
Own full verification signoff for PCIe Gen5/Gen6 Controller & Subsystem

Define verification strategy, execution plan, and signoff criteria

Review architecture, microarchitecture, and RTL specs

Create comprehensive verification plans covering:

Transaction Layer, Physical Layer, Data Link Layer, PIPE

SRIOV with large virtual functions

Recovery mechanisms

Map protocol features to testcases, assertions, coverage, scoreboards

Architect reusable UVM environments for IP, subsystem, and SoC

Drive functional, code, assertion, and cross coverage

Analyze coverage gaps and drive closure

Verify ControllertoPHY integration and PIPE compliance

Validate equalization, link training, recovery, speed/lane width changes

Collaborate closely with PHY, Analog, RTL, DFT, Firmware, PD, and Validation teams

Leadership Responsibilities
Lead and mentor verification engineers

Conduct verification reviews and audits

Drive schedules, planning, and execution tracking

Interface with customers and program management

Own verification signoff reviews

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