Why This Role Stands Out
This hybrid Analog Layout Engineer role offers a fantastic opportunity to contribute to cutting-edge chip designs using advanced process nodes, fostering significant career growth and skill development. You'll thrive here if you possess extensive experience with high-speed layouts and specific blocks like LDO, ADC, and SERDES, and are eager to work with industry-leading tools. Apply now to leverage your expertise and make a real impact in a dynamic environment.
Quick Overview
Job Description
Analog Layout Engineer
Bay Area, CA
Long term Contract
Exp : Minimum 8 years and above
Skill : 2nm, 3nm and 5nm process and high speed layout
Blocks : LDO ,ADC and SERDES
Tools : Cadence ,Virtuoso XL
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