Design Verification Engineer

Hello,

Hope you are doing great.

We have an immediate Requirements for these role

📌 Hiring: Design Verification Engineer

📍 Location: San Jose, CA

🕒 Job Type: Full-Time  

Job Summary:

We are seeking DV engineers to verify complex internal IP blocks such as compute engines, accelerators, and custom logic within SoC environments.

Key Responsibilities:

• Develop and maintain UVM-based verification environments
• Create test plans, testcases, and coverage models
• Perform functional verification of RTL designs
• Debug RTL and testbench issues
• Drive coverage closure (functional + code)

Required Skills:

• Strong hands-on with SystemVerilog and UVM
• Experience in block-level verification
• Good understanding of digital design fundamentals
• Experience with debug tools (Verdi, DVE, etc.)

Good to Have:

• Exposure to low-power verification (UPF)
• Experience with AMBA protocols (AXI/AHB/APB)

Rajesh (Thomas)

Senior Technical Recruiter

ICS Globalsoft Inc

1231 Greenway Drive | Ste 375 | Irving, TX 75038

E-mail: |

Direct Number: Ext: 127

NMSDC Certified | Certified Minority Business Enterprise (MBE), SBE | An E-Verify company

 According to Bill S.1618 Title III passed by the 105th US Congress, this message is not considered as Spam as we have included the contact information. If you wish to be removed from our mailing list, please respond with remove in the subject field. We apologize for any inconvenience caused.