Analog Layout Design Engineer

Analog Layout Design Engineer

We are currently looking for an Analog Layout Design Engineer for an onsite position in California with one of our clients. Based on your background, I wanted to reach out regarding this opportunity.

Key Requirements:

• Minimum 6+ years of experience in Analog Layout Design.
• Experience developing and leading complex IC layouts for high-speed applications in advanced CMOS FinFET technologies (7nm and below) at both block and chip levels.
• Thorough knowledge of industry-standard EDA tools such as Cadence, Mentor, and Synopsys.
• Experience with layout of high-performance analog mixed-signal blocks, including Transceivers, CMOS Drivers, High-Speed Data Converters, and PLLs.
• Expertise in floor planning, block-level routing, and top-level chip assembly.
• Knowledge of advanced layout techniques, including floor planning, layer generation, thermal-aware layout design, and electro-migration considerations.