Design Verification Engineer

Job Title: Design Verification Engineer

Location: San Jose, CA

Experience: 8+ Years

Type: Contract

Description:

This requirement is for a Senior Design Verification (DV) Engineer focused on verifying complex semiconductor IPs and SoCs before silicon fabrication. The client is looking for someone who can independently build verification environments, create test plans, and identify design bugs early in the development cycle.

 

Key Skills Required

·  8+ years of Design Verification experience in semiconductor/ASIC/SoC development.

·  Strong expertise in System Verilog.

·  Extensive experience with UVM (Universal Verification Methodology).

·  Experience verifying IP blocks and SoC-level designs.

·  Strong debugging and functional verification skills.

·  Scripting experience in Python, Perl, or Shell.

·  Ability to collaborate with RTL designers and architects to resolve design issues.

Experience writing:

o   Testbenches

o   Testcases

o   Assertions (SVA)

o   Functional coverage

 

Roles & Responsibilities:

·  Develop and maintain UVM-based verification environments.

·  Create verification plans based on design specifications.

·  Write System Verilog testbenches and assertions.

·  Execute simulations and analyze failures.

·  Debug RTL and verification issues.

·  Measure functional coverage and ensure verification closure.

·  Automate regression runs using scripting languages.

·  Work closely with design and architecture teams throughout the development cycle.

 

Must-Have Skills:

·  8+ years Design Verification

·  System Verilog

·  UVM

·  IP/SoC Verification

·  Functional Verification

·  Assertions (SVA)

·  Python/Perl/Shell scripting

·  Debugging RTL issues