Quick Overview
Seniority
Mid Senior
Work mode
Hybrid
Location
San Francisco, CA, United States
Posted
21 hours ago
Job Description
Job Title: Analog Layout Engineer
Location: San Francisco, CA (Bay Area)
Location: San Francisco, CA (Bay Area)
- Exp : Minimum 8 years and above
- Skill : 2nm, 3nm and 5nm process and high speed layout (MUST)
- Blocks : LDO ,ADC and SERDES
- Tools : Cadence ,Virtuoso XL
Similar jobs
- CI
Staff Hardware Systems Engineer
NewCHAOS Industries
El Segundo🇺🇸Yesterday401kCDNHTTPS+2Technology - AI
Hardware Test Engineer
NewAnduril Industries
Lexington🇺🇸YesterdayMATLABComplianceComputer Vision+10Technology - AM
Low Voltage Cabling Design Engineer, Network Infrastructure Desi with Security Clearance
Amazon
San Antonio, TX🇺🇸$111.3k - $186.1k/yrOn-site5 weeks agoFiberAWSHTTPS+3 - TT
PCB Layout Engineer
NewTHE TILTED CIRCLE LLC
Irvine, CA🇺🇸On-site21 hours agoAltiumPCB DesignEngineering - BS
Hardware Design Engineer with Security Clearance
NewBTS Software Solutions
Annapolis Junction, MD🇺🇸$180k - $265k/yrHybrid21 hours agoFPGAEngineering - AT
Senior EO/IR Systems Engineer with Security Clearance
Ataero
Patuxent River, MD🇺🇸Hybrid4 days agoTechnology